1. Field of the Invention
This invention relates to an improved method for forming lightly doped drain (LDD) regions in integrated circuit structures.
2. Description of the Related Art
The use of lightly doped drain (LDD) regions in VLSI MOS integrated circuit structures is well known to overcome electric field effects near the drain region which can cause short channel effects or punchthrough.
The formation of such a lightly doped drain region (LDD) between the channel and the more heavily and deeper doped conventional drain region spreads out the electric field which mitigates short-channel effects, reduces hot-carrier generation, and increases the junction breakdown voltage.
Oxide spacers, formed on the sidewalls of the gate electrode, have been utilized in the formation of such LDD regions in the substrate. For example, Bassous et al., in an article entitled "Self Aligned Polysilicon Gate MOSFETs with Tailored Source and Drain Profiles", proposed thermally oxidizing a polysilicon gate electrode and the silicon substrate followed by reactive ion etching to form oxide sidewalls or spacers on the side of the polysilicon gate electrode. Source and drain regions were then formed in the substrate by an N+ implantation with the oxide spacers shielding the regions in the substrate laterally adjacent the channel region in the substrate beneath the gate electrode. The oxide spacers were then stripped followed by an N- implant to form N- or lightly doped source and drain regions in the substrate between the N+ source and drain regions and the channel beneath the gate electrode.
Parillo et al., in an article entitled "A Versatile, High-Performance, Double-Level-Poly Double-Level-Metal, 1.2-Micron CMOS Technology", describe constructing MOS devices with LDD regions using, instead of the oxide spacer, a disposable polysilicon spacer which is formed on the sidewall of the gate electrode following which an N+ implant to form source and drain regions is performed. The polysilicon spacers are then removed and an N-implant is made resulting in N- LDD regions in the substrate between the N+ regions and the channel formed in the substrate beneath the gate electrode.
However, stripping such disposable polysilicon spacers from the structure could, in itself, cause further problems. Since they are said to be disposable, the polysilicon spacers presumably are separated from the polysilicon gate electrode by an oxide layer. If the quality of this oxide was not perfect, etchant used to remove the disposable polysilicon spacer might penetrate the oxide to attack the polysilicon gate. In addition, if there were pinholes in the oxide layer, which is formed over the polysilicon gate prior to deposition of the conformal layer of polysilicon used to form the polysilicon spacers, the two polysilicon layers may coalesce and subsequent RIE etching to form the spacer could etch through these areas instead of stopping on the oxide layer.
More recently, it has been recognized that the formation of LDD regions which results in an offset between the N+or P+source and drain regions and the gate electrode results in a significant reduction in current-drive capability and faster degradation rates. To remedy this, it has been proposed to laterally extend a thin portion of the polysilicon gate electrode, i.e., by forming the gate electrode in the shape of an inverted T.
In "A Novel Submicron LDD Transistor With Inverse-T Gate Structure", Huang et al. describe the formation of an MOS transistor with an LDD region wherein the polysilicon gate edge extends over the LDD region to the edge of the heavier doped drain region. The device is formed by not fully etching away the polysilicon layer used to form the gate electrode, leaving a thin polysilicon layer of about 50-100 nanometers. The substrate is then doped through this thin polysilicon layer to form the LDD regions. Conventional oxide spacers are then formed on the sides of the raised polysilicon gate after which the remainder of the thin polysilicon layer not beneath the oxide spacers is removed, leaving a T shaped polysilicon gate electrode. The conventional source/drain doping is then carried out with the oxide spacers shielding the previously formed LD regions. The thin polysilicon portions beneath the oxide spacers next to the gate electrode then act as extensions of the gate electrode to the conventional source and drain regions.
In "Impact of the Gate-Drain Overlapped Device (GOLD) for Deep Submicrometer VLSI", Izawa et al. describe the formation of an MOS device using a first thin layer of polysilicon over which an oxide etch stop layer is deposited before applying a second polysilicon layer. The upper polysilicon layer is then etched down to the oxide etch stop to form the gate electrode following which the substrate is lightly doped through the lower polysilicon layer to form an N- region in self-alignment with the gate. Oxide sidewall spacers on the sidewall of the gate electrode are then formed before doping with arsenic to form the N+ source and drain regions outside the oxide spacers.
In "A Self-Aligned LDD/Channel Implanted ITLDD Process With Selectively-Deposited Poly Gates for CMOS VLSI", Pfiester et al. describe formation of MOS transistors with LDD regions formed by first forming a thin polysilicon layer over a gate oxide layer and then depositing a thick LTO gate masking layer over the polysilicon layer. Windows are then opened in the LTO layer and polysilicon is selectively deposited to form the gate electrodes. The LTO layer is then removed leaving a continuous thin poly shelf with thicker poly B regions only over MOS channel regions. Selective N- and P- implantation is then carried out to form the LDD regions. Oxide sidewall spacers are then formed followed by removal of remaining exposed portions of the poly shelf to leave a T shaped polysilicon gate electrode. The structure is then subject to N+ and P+ implantation.
While the formation of such T-shaped polysilicon gate electrodes does permit formation of the desirable LDD regions in integrated circuit structures without forming offsets between the gate electrode and the source and drain regions of the active device, formation of the thin polysilicon lateral extension portions of the gate electrode is difficult from a production standpoint.
Chen et al. in an article entitled "Simple Gate-to-Drain Overlapped MOSFET's Using Poly Spacers for High Immunity to Channel Hot-Electron Degradation", suggests the formation of polysilicon spacers formed similarly to the prior art formation of oxide spacers, i.e., by depositing a layer of polysilicon followed by etching to leave a polysilicon spacer on the side of the gate electrode.
However, using this method still requires separate steps to deposit the polysilicon layer and then to etch the polysilicon layer to form the spacers. It would, therefore, be desirable to provide an improved and simplified method for forming such LDD regions in the substrate of an integrated circuit structure, without creating undesirable offsets between the gate electrode and the source and drain regions, by forming a gate electrode structure with polysilicon formed over LDD regions in the wafer substrate which eliminates difficult to produce T-shaped gate electrodes, as well as the need for a separate etching step after deposition of the polysilicon over the LDD regions.